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EPSON STYLUS TX110 RESET CODE
I would like to think that I can point to my present code as an example of what a newbie should do.
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If you don't clean house at least yearly, you begin to look at the old code and ask questions like 'did I DO THIS?' or 'Man, is this OLD CODE'. After your New_SBR has been running for a week/month/year you need to remove the old one, get rid of the Uprade condition on the new one. Once you get past 16 upgrades at a time, you need to clean stuff up! My single bits, used to switch between 'old method' logic and 'new method' logic are called Upgrade, a boolean array of maybe 10 - 16 bits.
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I like using a NOP in the first rung, then tying a big comment to it to explain that the logic is not executing but is kept for reference as mentioned, multiple OTEs to a single bit give warnings and make experienced programmers 'CRAZY' as they try to figure out what you did and why a separate unscheduled task works fine as well to be paranoid, add a TND or RET as the first rung of the backup copy so that the subroutine returns immediately after being called instead of executing if the subroutine is not called, you don't have to worry about 'commenting out' the code - it is not executing So far I agree with pretty much all of the comments. Sorry about asking before trying but I would like to find out also if there consequences I don't know about if it actually works. I could keep back up ACD with one of those routines in each but then I would lose online state of the XIC, XIO bits in the back up. What I am trying to do is to do major changes to the subroutine, but I want to keep original for reference to troubleshoot. I'm trying to do something similar with RSLogix 5000 V20.12, 1769-元6ERM PLC. If it's called at all - even if everything is AFI'd out - you're Not Gonna Have A Good Time.Īlso, make sure you clean up after yourself when you've finished and delete the backup logic, because duplicating OTE's is in general bad practice, confusing, and makes me grumpy :) Is that possible?Ĭertainly possible - but ONLY if you do not call the routine that contains the logic you want to ignore (as you've done) or you use a JMP to skip over it. I want the PLC to only turn on/off the same OTE bits in one subroutine and ignore them in the backup. I know that AFI will turn off OTE bit, rung in false condition will also turn off OTE bit.īoth subroutines have the same OTE bits. I'm pretty certain it wasn't as far back as v20, so yes, even if your routine is not being scanned you will still have the green rails. Perhaps v27 or 28, someone like Geospark will probably know off the top of his head. I believe that it was only in quite a recent version of Logix Designer that they added the feature to turn off the "green rails" if the routine is never being called. Yet the backup still have green rails when it doesn't have JSR to it from main. I've made a backup copy of it with different name that is does not have a JSR to it from main routine. I would not advocate putting the deleted rung into "Test Edits" mode for anything longer than your own online session! Or delete the rung from the program completely. Or you could simply remove the rung from the subroutine file into another that isn't JSR'd from anywhere. You can, of course, make the JMP conditional so you can "switch" the rung in or out. I would prefer to do this over moving the rung to the end of the file and using a TND in front of it. If you really, really, want the rung to stay in the executed code, but be ignored, then you will have to place a JMP in front of it it to a LBL rung after it. The ONLY way to achieve this is to stop the rung being scanned. Neither the MCR or AFI (or equivalent) will "comment out" a rung so that it is ignored. The AFI will do exactly the same as a false MCR zone - see the above description. Putting an AFI on a rung does not stop the processor executing the rung, i.e. I don't class this as "ignoring the code".Ģ. This will have the effect of turning OFF all non-retentive outputs, resetting TONs, freezing RTOs, starting TOFs timing, and preconditioning false-to-true transition triggered instructions to execute again when the MCR is made true again. If you place an MCR zone around a rung of logic, then when the opening MCR instruction is FALSE, the following rungs are executed as normal, but the rung-in condition (the power-rail, if you like) is made FALSE. MCR zoning a rung does not stop the processor executing the rung, i.e. Let us all get several things absolutely straight, there is too much discussion of MCR, AFI, and custom "Always False Bits" taking place.īernie hit the nail firmly on the head earlier.ġ.